module det_seq(clk, rst, d_in, hit);
input      clk;
input      rst;
input      d_in;
output reg hit;

parameter start = 3'b000,
             s0 = 3'b001,
             s1 = 3'b010,
             s2 = 3'b011,
             s3 = 3'b100,
             s4 = 3'b101,
             s5 = 3'b110;
          
reg [2:0] cur_state;          
reg [2:0] nxt_state;          

always @(posedge clk or posedge rst) 
begin
   if (rst)
      cur_state <= start;
   else
      cur_state <= nxt_state;
end   

always @(*)
begin
   hit = 1'b0;
   case (cur_state)
      start: begin
         if (!d_in)
            nxt_state = s0;
         else
            nxt_state = start;
      end    
      s0: begin
         if (d_in)
            nxt_state = s1;
         else
            nxt_state = s0;
      end    
      s1: begin
         if (!d_in)
            nxt_state = s2;
         else
            nxt_state = start;
      end    
      s2: begin
         if (d_in)
            nxt_state = s3;
         else
            nxt_state = s0;
      end    
      s3: begin
         if (d_in)
            nxt_state = s4;
         else
            nxt_state = s2;
      end    
      s4: begin
         if (!d_in)
            nxt_state = s5;
         else
            nxt_state = start;
      end    
      s5: begin
         if (!d_in)
            nxt_state = s0;
         else
            nxt_state = s1;
         hit = 1'b1;
      end
      default: 
         nxt_state = start;
   endcase         
end

endmodule          